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Hardware design has revolutionized the way the world interacts. Device capabilities continue to sky rocket today and designers must explore more ways to improve time to market. Debugging problems costs time and threatens stellar performance. Trial and error can push time to market to infinity and beyond.
Training fills the spaces between inefficiency and productivity. With Logtel training, your engineers will find all the knowledge and skills necessary to go ahead and design the future. Advanced courses help you push the outer limits of the latest technologies. Logtel is also the Authorised Training Provider (ATP) in Israel and Turkey training Xilinx customers and partners.
Browse our variety of topics below. Logtel can also tailor-develop a training plan that fits your organization's current needs for the diverse background of your engineers. In-House sessions are offered to our clients on-site so you maintain your employee productivity throughout the training program. 'Public' training programs allow your selected employees starting from a single individual - to join training programs taking place at a Logtel training center.
For more training opportunities, please check our Catalog or contact us for details.
| Course name | Coming Date | Duration (days) | More info | ||||||
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| FPGA TOOLS | |||||||||
| Debugging Techniques using the ChipScope Protool | Call | 2 |
Click here
As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.
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| Designing with the PlanAhead tool | 27/03/12 | 3 |
Click here
Learn to increase design performance and achieve repeatable results, plan an I/O pin layout, and implement by using the PlanAhead software tool. Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool, synthesis and project tips, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope Pro tool, and design preservation with partitions.
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| Designing with the TMR Tool | Call | 2 |
Click here
The TMR Solution for Next-Generation Space Applications
New approaches have been developed to address Single-Event Upsets (SEUs) and Single-Event Transients (SETs) in re-programmable logic devices including Virtex™, Virtex-II, Virtex-II Pro and Virtex-4. The XTMR methodology along with scrubbing provides full SEU and SET immunity for any high reliability Virtex FPGA. This course provides a solid working knowledge of the Xilinx TMRTool and the XTMR design flow. This course also offers background and insight on the historic SEU, SET, and SEFI challenges that designers face when deploying any electronic circuitry in space. The focus of the course is the unique challenges that user-programmable FPGAs present and how TMRTool greatly simplifies the TMR process for a Xilinx FPGA. Throughout the course, you will explore the key features and capabilities of the TMRTool and understand possible TMR tradeoffs.
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| FPGA Architecture and ISE Features | Call | 2 |
Click here
ISE Design Tool Flow provides the overall context and framework for the development cycle of FPGAs. For those uninitiated to FPGA design, this course will arm you with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design now.
The flow will take you from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced. Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. [Close] |
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| ADVANCED FPGA | |||||||||
| Advanced FPGA Implementation | Call | 3 |
Click here
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this three-day training and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.
FPGA 4 |
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| Designing for Performance | 31/03/12 | 2 |
Click here
Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
This course focuses on the Spartan-6 and Virtex-6 architectures.
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| Designing with Multi-Gigabit Serial I/O | Call | 3 |
Click here
Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT FPGA or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
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| Designing with the Spartan-6 and Virtex-6 families | 26/02/12 | 3 |
Click here
Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced. This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
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| Designing with the Virtex-5 LX & LTX FPGA | Call | 1 |
Click here
Interested in learning how to utilize Virtex™-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device. Topics covered include a Virtex-5 FPGA overview, new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources.
Additionally, the new resources available in the LXT platform (EMAC, PCI Express, and GTP) are discussed. A combination of modules and labs allow for practical hands-on application of the principles taught.
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| Designing with the Xilinx 7 Series Families | 14/05/12 | 2 |
Click here
Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in this popular device family. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express® technology, analog to digital converters and gigabit transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
FPGA3 |
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| Migrating to Xilinx | Call | 2 |
Click here
This course focuses on providing ASIC/ FPGA experienced designers with the Xilinx tool-set flow. Current designers will get familiar with the various Xilinx tools, (ISE, XST, MAP, Place and Route, Trace…) and design techniques. HDL inference of FPGA resources and coding examples are provided. The course highlights the Virtex-IV family though most concepts can also be applied to Virtex-based designs. HDL inference of FPGA resources and coding examples are provided.
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| Partial Reconfiguration Tools & Techniques | 15/02/12 | 2 |
Click here
This course demonstrates how to use the ISE®, PlanAhead™, and Embedded Development Kit (EDK) software tools to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
This course covers both the tool flow and mechanics of successfully creating a PR design. It also describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications.
FPGA 4 |
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| Tips and Tricks for FPGA Designers | 05/05/12 | 1 |
Click here
Attending the Tips & Tricks for FPGA Design class will enrich your knowledge in several aspects of the FPGA design world. This 1 day seminar will enable you to get familiar with new aspects and problems you may encounter during your project flow. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, lower the design risk and development costs.
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| HARDWARE DEFINITION LANGUAGES | |||||||||
| Advanced Verilog for Designers | Call | 2 |
Click here
This comprehensive 2 days course provides complete and integrated training program. It is structured as a comparison between traditional Verilog 1995 and newer Verilog standards – 1364-2001 and 1800-2005 System Verilog. The goal of this course is to fulfill needs and requirements engineers, who want to exploit wide breadth of System Verilog features for both design and basic testbench.
Intermediate to Advanced
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| Advanced VHDL | Call | 2 |
Click here
VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice. This training builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.
[Close] |
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| Designing with Verilog | 04/03/12 | 4 |
Click here
This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.
FPGA1
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| Expert VHDL – Advanced Level | 07/02/12 | 6 |
Click here
VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies. [Close] |
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| Fast-track Verilog for VHDL Users | 02/06/12 | 2 |
Click here
Verilog for VHDL Users is an intensive 2-day course, converting knowledge of VHDL to practical Verilog skills.
Contrasting Verilog and VHDL, this course demonstrates similarities and highlights differences between two hardware description languages and their associated design flows. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. Labs comprise about 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] |
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| SystemVerilog for Design and Verification | 20/05/12 | 4 |
Click here
This comprehensive 4-days hands-on intensive course provides complete and integrated training program. It provides the participants with a deep knowledge of 1800-2005 SystemVerilog. The goal of this course is to fulfill the needs and requirements of engineers wanting to exploit the breadth of SystemVerilog features for both design and verification.
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| VHDL for FPGA | 06/05/12 | 4 |
Click here
VHDL training by Doulos is the industry standard training courses teaching the application of VHDL for FPGA and ASIC design. It is fully updated and restructured to reflect current best practice.
This trainingprepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. Because Doulos is independent, delegates can usually use their choice of design tools during the workshops. Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. [Close] |
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| EMBEDDED DESIGN | |||||||||
| Advanced Features and Techniques of Embedded Systems Design | 14/04/12 | 2 |
Click here
Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary training to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system. This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Labs use demo boards in which designs are downloaded and verified.
EMB HW 4 |
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| Embedded Linux Design on MicroBlaze Processor – with PetaLinux SDK | 20/03/12 | 2 |
Click here
This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded PetaLinux SDK operating system on a Xilinx MicroBlaze™ processor development board. The course offers students hands-on experience on building the environment and booting the system using a basic, single-processor System on Chip (SoC) design with PetaLinux SDK on the MicroBlaze processor.
This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow. [Close] |
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| Embedded Open-Source Linux Development | Call | 3 |
Click here
This intermediate-level course provides embedded systems developers with experience in creating an embedded open-source Linux operating system on a Xilinx development board. The course offers students hands-on experience from building the environment to booting the system using a basic, single-processor System on Chip (SoC) design with Linux 2.6 from the Xilinx kernel tree. This course introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow
Intermediate
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| Embedded Software Development | 20/02/12 | 2 |
Click here
This two-day course introduces you to software design and development for Xilinx embedded processor systems. You will learn the basic tool use and concepts required for the software phase of the design cycle, after the hardware design is completed.
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| Embedded Systems Development | 19/02/12 | 3 |
Click here
Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, AXI interconnect, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.
EMB HW 3 |
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| Essentials of Microprocessors | 28/04/12 | 2 |
Click here
Learn what makes microprocessors tick! This class offers insights into all major aspects of microprocessors, from registers through coprocessors and everything in between. Differences between RISC and CISC architectures are explored as well as the concept of interrupts. A generic microprocessor is programmed and run in simulation to reinforce the principles learned in the lecture modules. The student will leave the class well prepared for the Xilinx Zynq training curriculum.
Embedded 1 |
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| How to Design Xilinx Embedded Systems in 1 Day | 01/03/12 | 1 |
Click here
The workshop introduces you to fundamental embedded design concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of Xilinx embedded tools, IP, and the Embedded Targeted Reference Design (TRD). Design examples and labs are drawn from the Embedded TRD.
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| DSP DESIGN | |||||||||
| DSP Design Using System Generator | Call | 2 |
Click here
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.
Intermediate |
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| DSP Implementation Techniques for Xilinx FPGAs | 15/05/12 | 2 |
Click here
This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.
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| How to Design a Xilinx Digital Signal Processing System in 1 Day | Call | 1 |
Click here
The workshop introduces you to fundamental DSP concepts, algorithms, and techniques for implementation in Xilinx FPGAs. Design examples and labs are drawn from several common applications spaces, including wireless communications, video, and imaging.
Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. The material is also complementary to the Avnet SpeedWay Design Workshop on FPGA-Based System Design with High-Speed Data Converters. Level: DSP 3 [Close] |
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| Signal Processing Applications and Algorithms | 19/02/12 | 4 |
Click here
Attending the Signal Processing Applications and Algorithms class will give you a theoretical background on Signal Processing Algorithms and demonstrates Applications used in the industry. You will be mastering the MATLAB® and Simulink® tools during the training in the lab exercises embedded into the training
[Close] |
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| VLSI-DSP for the ASIC and FPGA Engineer | Call | 3 |
Click here
Many applications in today's technological world require fast DSP processing. Anything from physical layer processing in communication infrastructure to extraordinary image and sound processing in medical equipment. DSP is a unique area in VLSI design. There are many ways to implement the same DSP algorithm, though the efficient implementation may not be so obvious and would usually require particular expertise.The course introduces important basic concepts in DSP designing, surveys a variety of structures and advanced DSP implementations in VLSI. Level:Intermediate [Close] |
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| PCB WORLD | |||||||||
| EMI/EMC and ESD Training | Call | 3 |
Click here
In modern electronics, component size continues to decrease and complexity to increase. Electrostatic and magnetic fields and their interactions are becoming increasingly important. As problems have arisen, creative solutions had to be developed. An understanding of the principles and developments in this growing field is essential to many individuals in electronics industries
[Close] |
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| How to Design a High-Speed Memory Interface | 15/02/12 | 2 |
Click here
This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using Spartan®-6 and Virtex®-6 FPGAs. Additionally, you will learn about the tools available for high-speed memory interface design, implementation, and debugging.
Connectivity 3 |
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| How to Design a Xilinx Connectivity System in 1 Day | 29/02/12 | 1 |
Click here
This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of transceivers, PCIe® technology, memory interfaces, and Ethernet MACs. Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. Design examples and labs are drawn from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights use of the MGT.
Connectivity 2 |
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| Power & Signal Integrity for Board Design Using HyperLynx | Call | 3 |
Click here
Learn when and how to apply power & signal integrity techniques to high-speed interfaces between components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
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| Signal Integrity and Board Design Using HyperLynx | 18/03/12 | 3 |
Click here
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.
Connectivity 3 |
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| Tips & Tricks For Board Designers | 04/04/12 | 1 |
Click here
Attending the Tips & Tricks for Board Design class will enrich your knowledge in several features of current board design. This 1 day seminar will familiarize you with new aspects and problems you may encounter during project development. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to design faster, shorten development time, lower development costs and lower design risk.
Intermediate |
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| HARDWARE ENRICHMENT | |||||||||
| Active-HDL 8.2 Trainings | Call | 3 |
Click here
Active-HDL is an integrated easy-to-use FPGA Design and Simulation solution, providing a robust design creation tool suite, a high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and over 87 popular EDA tools, all-in-one common environment.
The Active-HDL 8.2 Training will provide you with the know-how for best practice of Active-HDL via hands-on experience. [Close] |
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| ASIC Prototyping with FPGA | Call | 2 |
Click here
The process of ASIC design and production becomes more and more expensive.
NRE may be millions of $$. Time to market is always critical and cycle needed to be shorter. Although good verification environment is essential for ASIC success, it may not be enough. Due to very long simulation cycle times , lack of manpower , timing issues , uncovered system scenarios , lack of software drivers etc. ASIC prototyping in FPGA increases significantly the probability of ASIC 1st time pass. However, there are technology differences between ASIC and FPGA that should be taken into consideration. This course will emphasize the differences and how they should be handled [Close] |
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| From Network Concept to Working Silicon | 19/02/12 | 2 |
Click here
Over the years the use of communication networks has not only increased but also changed dramatically. Carriers today are aiming for a converged network that will supply data, audio and video communication on the same network infrastructure, providing a wide variety of new applications alongside the classical telephony, internet surfing, and TV broadcasting. To meet that goal the routers and switches in these networks and their underlying HW engines must improve. The HW engines are required to do diverse tasks from parsing and editing the packets, through forwarding them to scheduling them. Applying the right mechanisms for these diverse, demanding tasks requires an understanding in both networking and chip design. This course will discuss the context between the two fields with samples of Xilinx' implementations.
[Close] |
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| PCI Express Protocol GEN1, GEN2 and GEN3 | 11/03/12 | 3 |
Click here
PCI Express is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.
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| Practical Aspects of Electronic Module Development & Production Workshop | Call | 1 |
Click here
Introduction to all Electronic Module Development Variables and there Implication on the product design, for:
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| Principles of Digital Image Processing | Call | 4 |
Click here
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| RTOS & VxWorks 6.xx | Call | 5 |
Click here
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| The Secrets of Electronics in three days | Call | 3 |
Click here
This course presents the essentials of Electronics engineering and Hardware Design for software engineers. The course is a complete tour of the fundamentals of electrical engineering. It will enable the software engineer that works with an electronics engineer’s better communicate and understand the electrical engineering when working on a common project. The course presents examples of all the learning material.
Fundamental
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| USB 3.0 System Architecture | Call | 2 |
Click here
The USB 3.0 (SuperSpeed) architecture is a third-generation, high-performance USB standard used to interconnect peripheral devices in computing platforms. USB 3.0 has been designed to consumer and high-end PCs, provides a greater than 10x increase in performance over the high-speed performance of USB 2.0.
The Complete USB 3.0 is intensive 2- day course designed for the hardware or software engineers. Attendees will learn about the significant changes made in the USB 2.0 protocol. The training will feature in-depth coverage of the USB 3.0’s Physical, Data Link, and Protocol Layers. The changes in flow control and power management will be examined. The course provides practical examples of USB 3.0 transactions and error conditions. The rules required for a host and device to be specification compliant will be indentified.
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| LONG TERM TRAINING (LTT) | |||||||||
| BoardDesignExpert | 12/02/12 |
Click here
Duration:
120 Hours
[Close] |
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| FPGAXpert | 26/03/12 |
Click here
Duration:
120 Hours
[Close] |
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| MATLAB | |||||||||
| Advanced Matlab | Call | 2 |
Click here
This two-day course shows attendees how to analyze signals and design signal processing systems using MATLAB® and Signal Processing Toolbox™. Parts of the course will also use Filter Design Toolbox™.
Topics include:
[Close] |
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| MATLAB for Image Processing | Call | 2 |
Click here
This two-day course shows how to perform various image processing techniques using the Image Processing Toolbox. The course explores the different types of image representations, how to enhance image characteristics, image filtering, and how to reduce the effects of noise and blurring in an image. It also introduces different methods used to extract features and objects within an image, image registration, and a few techniques for reconstructing images/objects.
[Close] |
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| MATLAB for Signal Processing | Call | 2 |
Click here
This two-day course shows attendees how to analyze signals and design signal processing systems using MATLAB® and Signal Processing Toolbox™. Parts of the course will also use Filter Design Toolbox™.
Topics include:
[Close] |
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| MATLAB Fundamentals | Call | 3 |
Click here
MATLAB Fundamentals is a three-day course that provides a comprehensive introduction to the MATLAB technical computing environment. This course is intended for beginning users and those looking for a review. No prior programming experience or knowledge of MATLAB is assumed, and the course is structured to allow thorough assimilation of ideas through hands-on examples and exercises. MATLAB competency is developed in a natural way, with an emphasis on practical application. Themes of data analysis, visualization, modeling, and programming are explored throughout the course. Topics Include:
[Close] |
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| Simulink for Communication Systems | Call | 1 |
Click here
Using hands-on examples, this one-day course demonstrates the use of MathWorks products to design common communication systems. The emphasis is on designing end-to-end communication systems using Simulink®, Communications Blockset™, and Signal Processing Blockset™. Topics include:
[Close] |
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| Simulink for System and Algorithm Modeling | Call | 2 |
Click here
This course is for engineers who are new to system and algorithm modeling and design validation in Simulink®. It demonstrates how to apply basic modeling techniques and tools to develop Simulink block diagrams. Topics include:
[Close] |
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