This course demonstrates how to use the ISE®, PlanAhead™, and Embedded Development Kit (EDK) software tools to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
This course covers both the tool flow and mechanics of successfully creating a PR design. It also describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications.
Level:
FPGA 4
Skills Gained:
After completing this training, you will be able to:
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Build and assemble a Partially Reconfigurable system
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Define PR regions and reconfigurable modules with the PlanAhead software
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Generate the appropriate bitstreams targeting Platform Flash and System ACE™ interface tool files to support on-board partial bitstream storage
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Use the ChipScope™ Pro tool to monitor/debug the ICAP component
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Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
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Implement a PR system using the following techniques:
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Direct JTAG connection
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HDL state machines
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Timing constraints and analysis
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Microprocessor-based designs
Recommended Courses:
Embedded Systems Development course
Essential Design with the PlanAhead Analysis and Design Tool course
Advanced Design with the PlanAhead Analysis and Design Tool
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need of partial reconfiguration techniques.