Intermediate
FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.
ISE Design Suite: Logic System Edition 14.1
Architecture: 7 series FPGAs*
Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import an RTL design into the PlanAhead software so that you can synthesize, implement, perform timing analysis, view logical and device resources, and generate a bitstream. Also introduces the PlanAhead software's environment and views.
Lab 2: Assigning I/O Pins – Introduces the PlanAhead software’s pin planning environment for performing I/O pin assignment. You will create a pin planning project, import and export I/O ports lists, create I/O ports and interfaces, run a DRC and SSN noise analysis, examine clock logic placement, and make pin assignments.
Lab 3: CORE Generator Tool Integration – Illustrates the integration of the CORE Generator software with the PlanAhead software. You will customize and integrate a core, explore the IP Catalog, and view the generated core with the Schematic viewer.
Lab 4: PlanAhead Software Review – Illustrates the steps you take to import source HDL files into the PlanAhead tool and synthesize, implement, and analyze the results. Also introduces the PlanAhead tool environment and views.
Lab 5: RTL Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations, RTL power estimations, and run an RTL Design Rule Check (DRC).
Lab 6: Placing Dedicated Resources – Introduces the methods for assigning location constraints to dedicated hardware resources. Demonstrates how to assign dedicated clocking resources, work with multi-function I/O pins, and complete a SSN noise analysis.
Lab 7: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
Lab 8: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.
Lab 9: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope Pro tool, cores, and Set Up ChipScope Wizard.
Lab 10: Tcl Commands – Use the Tcl interface in the PlanAhead software.for debugging designs with the ChipScope Pro cores and tools.
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