This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level:

FPGA1

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Basic digital design knowledge

Software Tools:

ISE Design Suite: Logic or System Edition 13.1

Hardware:

Demo board: Spartan-6 FPGA SP605 board

Skills Gained:

After completing this training, you will be able to:

• Write RTL Verilog code for synthesis

• Write Verilog test fixtures for simulation

• Create a Finite State Machine (FSM) by using Verilog

• Target and optimize Xilinx FPGAs by using Verilog Use enhanced Verilog file I/O capability

• Run a timing simulation by using Xilinx Simprim libraries

• Create and manage designs within the ISE software design environment

• Download to the Spartan-6 FPGA SP605 demo board